?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b rfp4n100, RF1S4N100SM 4.3a, 1000v, 3.500 ohm, high voltage, n-channel power mosfets the rfp4n100 and rfp4n100sm are n-channel enhancement mode silicon gate power field effect transistors. they are designed for use in applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. this type can be operated directly from an integrated circuit. formerly developmental type ta09850. features ? 4.3a, 1000v r ds(on) = 3.500 ? uis rating curve (single pulse) -55 o c to 150 o c operating temperature related literature - tb334 ?guidelines for soldering surface mount components to pc boards? symbol packaging jedec to-220ab jedec to-263ab ordering information part number package brand rfp4n100 to-220ab rfp4n100 RF1S4N100SM to-263ab f1s4n100 note: when ordering, use the entire part number. g d s gate drain (flange) source drain drain (flange) gate source data sheet january 2002
?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b absolute maximum ratings t c = 25 o c, unless otherwise specified rfp4n100, RF1S4N100SM units drain to source breakdown voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ds 1000 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr 1000 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d 4.3 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm 17 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20 v single pulse avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .e as (see uis soa curve) (figures 4, 14, 15) mj maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d linear derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 1.2 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. t j = 25 o c to 125 o c. electrical specifications t c = 25 o c, unless otherwise specified parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 10) 1000 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a2-4v zero gate voltage drain current i dss v ds = 1000v, v gs = 0v --25 a v ds = 800v, v gs = 0v, t c = 150 o c - - 100 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 2.5a, v gs = 10v (figures 8, 9) - - 3.500 ? turn-on delay time t d(on) v dd = 500v, i d 3.9a, r gs = 9.1 ?, r l = 120 ? ) --30ns rise time t r --50ns turn-off delay time t d(off) - - 170 ns fall time t f --50ns total gate charge (gate to source + gate to drain) q g(tot) v gs = 20v, i d = 3.9a, v ds = 800v (figure 13) - - 120 nc thermal resistance junction to case r jc - - 0.83 o c/w thermal resistance junction to ambient r ja --62 o c/w source to drain diode specifications parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = 4.3a - - 1.8 v reverse recovery time t rr i sd = 3.9a, di sd /dt = 100a/ s - - 1000 ns notes: 2. pulse test: pulse width 80 s, duty cycle 2%. 3. repetitive rating: pulse width limited by maximum junction temperature. rfp4n100, RF1S4N100SM
?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b typical performance curves t c = 25 o c, unless otherwise specified figure 1. normalized power dissipation vs ambient temperature figure 2. maximum cont inuous drain current vs case temperature figure 3. forward bias safe operating area fi gure 4. unclamped i nductive switching soa figure 5. output characteristics fig ure 6. saturation characteristics t a , ambient temperature ( o c) power dissipation multiplier 0.0 0 25 50 75 100 15 0 0.2 0.4 0.6 0.8 1.0 1.2 125 4.5 3.0 1.5 0 25 50 75 100 125 15 0 t c , case temperature ( o c) i d , drain current (a) 4.0 1.0 0.5 3.5 2.5 2.0 110 100 100 0 v ds , drain to source voltage (v) 100 10 1 0.1 0.01 i d , drain current (a) by r ds(on) area may be limited operation in this rfp4n100, RF1S4N100SM 10 s 100 s 1ms 10ms t c = 25 o c t j = max rated single pulse dc 0.01 0.10 1 10 t av , time in avalanche (ms) 100 10 1 i as , avalanchecurrent (a) idm starting t j = 25 o c starting t j = 150 o c if r = 0 t av = (l)(i as ) / (1.3 x rated bv dss - v dd ) if r 0 t av = (l/r) in ((i as x r) / (1.3 x rated bv dss - v dd ) + 1) 0 100 200 300 400 50 0 v ds , drain to source voltage (v) 10 8 6 4 2 0 i d , drain current (a) v gs = 6v v gs = 5v v gs = 4v v gs = 10v pulse duration = 80 s duty cycle = 0.5% max 0 102030405 0 v ds , drain to source voltage (v) 10 8 6 4 2 0 i d , drain current (a) v gs = 10v pulse duration = 80 s duty cycle = 0.5% max v gs = 6v v gs = 5v v gs = 4v rfp4n100, RF1S4N100SM
?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b figure 7. transfer characteristics figure 8. drain to source on resistance vs drain current figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized drain to source breakdown voltage vs junction temperature figure 11. capacitance vs drain to source voltage figure 12. drain current vs source to drain diode voltage typical performance curves t c = 25 o c, unless otherwise specified (continued) 02 4 6 8 v gs , gate to source voltage (v) 5 4 3 2 1 0 i ds(on) , drain to source current (a) pulse duration = 80 s duty cycle = 0.5% max v ds = 15v 150 o c 25 o c 6 5 4 3 2 1 0 02468101 2 v gs = 10v i d , drain current (a) r ds(on) , drain to source pulse duration = 80 s on resistance ( ? ) duty cycle = 0.5% max normalized drain to source 3.0 2.0 1.5 1.0 0.5 -50 0 50 t j , junction temperature ( o c) 100 2.5 v gs = 10v, i d = 4.3a 15 0 on resistance pulse duration = 80 s duty cycle = 0.5% max normalized drain to source 1.3 1.1 1.0 0.9 0.8 -40 0 40 t j , junction temperature ( o c) 120 1.2 80 i d = 250 a 16 0 breakdown voltage 11010 0 3000 2500 2000 1500 1000 500 0 c, capacitance (pf) c iss c oss c rss v ds , drain to source voltage (v) v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 0 0.3 0.6 0.9 1.2 v sd , source to drain voltage (v) 100 10 1 0.1 i d , source to drain current (a) t j = 150 o c t j = 25 o c 1. 5 rfp4n100, RF1S4N100SM
?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b figure 13. gate to source voltage vs gate charge test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. switching time test circuit figure 17. resistive switching waveforms typical performance curves t c = 25 o c, unless otherwise specified (continued) 0 2040608 0 q g , total gate charge (nc) v gs , gate to source voltage (v) 0 4 8 12 16 i d = 3.9a v ds = 200v v ds = 100v v ds = 400v t p v gs 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t on t d(on) t r 90% 10% v ds 90% 10% t f t d(off) t off 90% 50% 50% 10% pulse width v gs 0 0 rfp4n100, RF1S4N100SM
?2002 fairchild semiconductor corporation rfp4n100, RF1S4N100SM rev. b figure 18. gate charge test circuit figure 19. gate charge waveforms test circuits and waveforms (continued) r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = 2v q g(10) v gs = 10v q g(tot) v gs = 20 v v ds v gs i g(ref) 0 0 rfp4n100, RF1S4N100SM
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
|
